/*
#include "softSerialTransmitter.h"
#include <avr/io.h>
#include <avr/interrupt.h>

#define DATAPORT PORTC
#define DATABIT 0
#define DATADDR DDRC

// What was done LAST time.
#define STARTBIT 0
#define DATABIT0 1
#define DATABIT7 8
#define STOPBIT  9
#define STOPPED 10

volatile uint8_t t2Status = WAITSTART;
uint8_t t2Data;

#define BUFSIZ 32
#define MASK (BUFSIZ-1)

volatile uint8_t t2BufIn;
volatile uint8_t t2BbufOut;
volatile uint8_t t2Bbuffer[BUFSIZ];

uint8_t t2SSavailable(void) {
	return (t2BufIn-t2BufOut) & MASK;
}

uint8_t t2SSspace(void) {
	return (t2BufOut-t2BufIn-1) & MASK;
}

void t2SSput(uint8_t data) {
	if (t2Status==STOPPED) {
		t2Data = data;
		t2Status = STARTBIT;
		DATAPORT &= ~(1<<DATABIT);
		// start timer
		TCNT2 = 0;
		TCCR2B = 1;
	} else {
		t2Buffer[t2BufIn] = data;
		t2BufIn = (t2BufIn+1) & MASK;
	}
}

uint8_t t2SSget(void) {
	uint8_t result = t2Buffer[t2BufOut];
	t2BufOut = (t2BufOut+1) & MASK;
	return result;
}

void initTimer2SoftSerialTransmitter(uint32_t baudRate) {
	// Set up the timer speed and port as output.
	// Assume we have to work with 38400 and 57600 baud. That is 208 clock cycles per bit 
	// (wow that is fast!). We can assume timers run with 1:1 prescale.
	// Set timer to CTC and enable interrupt (but do not start timer).
	TCCR2A = 1<<WGM21;
	TIMSK2 |= (1<<OCIE2A);
	OCR2A = F_CPU / baudRate;
	// Do NOT start timer.
	TCCR2B = 0;
	DATAPORT |= (1<<DATABIT); // stop 
	DATADDR |= (1<<DATABIT);
}

ISR(TIMER2_COMPA_vect) {
	if (t2Status==STOPBIT) {
		if (t2SSavailable()) {
			DATAPORT &= ~(1<<DATABIT); // send start bit.
			t2status = STARTBIT;
			data = t2SSget();
		} else {
			// no data to send, stop the train.
			t2Status = STOPPED;
			TCCR2B = 0;
		}
	} else if (t2Status==DATABIT7) {
		// Send stop bit.
		DATAPORT |= (1<<DATABIT);
	} else {
		// a data bit.
		uint8_t databit = data & 1;
		t2Data = t2Data>>1;
		if (databit) {
			DATAPORT |= (1<<DATABIT);
		} else {
			DATAPORT &= ~(1<<DATABIT);
		}
		t2Status++;
	}
}
*/
